1. Field of the Invention
The present invention relates to memory fabrication. More specifically, the present invention relates to a method for manufacturing non-volatile memory cells.
2. Description of the Prior Art
Computer storage media technology is evolving rapidly. While hard drives and CD-ROMs will still be around for years to come because of their high capacity and low cost, new forms of storage are constantly being developed. One technology that appears to have distinct advantages over conventional forms of storage is flash memory. Like conventional storage systems, flash memory is nonvolatile, requiring no power to maintain the stored information, and rewriteable.
FIG. 1 is a sectional schematic diagram illustrating a prior art non-volatile memory cell structure1. As shown in FIG. 1, prior art non-volatile memory cell structure1 includes a substrate 10, a tunneling oxide layer 11 formed on the substrate 10, a floating gate 12 formed on the tunneling oxide layer 11, a dielectric layer 13, and a control gate 14. A drain region 15 and a source region 16 are provided in he substrate 10.
FIG. 2 illustrates another prior art non-volatile memory cell structure 2 having a split gate for improving work performance and reliability of the non-volatile memory cell structure 2. As shown in FIG. 2, the prior art non-volatile memory cell structure 2 includes a substrate 20, a tunneling oxide layer 21, a floating gate 22, a dielectric layer 23, a control gate 24, a polysilicon spacer 25, and an erase oxide layer 26. A drain region 27 and a source region 28 are provided in the substrate 20. The polysilicon spacer 25 functions as a split gate which is isolated from the substrate 20 and the stacked gate structure consisting of the floating gate 22 and the control gate 24 by the erase oxide layer 26.
The manufacturing process for the above-mentioned prior art non-volatile memory cell structure 2 is complex. To manufacture the prior art non-volatile memory cell structure 2 as set forth in FIG. 2, a first polysilicon layer is deposited over the substrate 10, which is thereafter patterned and etched to form the floating gate 22. After this, a second polysilicon layer is deposited and is then patterned and etched to form the control gate 24. After the formation of the control gate 24, a third polysilicon layer is deposited thereon. The third polysilicon layer is subjected to an etching back process to form the split gate structure 25. Therefore, it needs three polysilicon layers to complete the prior art non-volatile memory cell structure 2.
However, the above-mentioned prior art non-volatile memory cell structure is quite not compatible with the manufacturing process for the peripheral logic circuit. It is well known that, in most cases, the peripheral logic circuit includes CMOS single-poly transistors. The memory cell structure determines the degree of integration between the manufacturing process for the non-volatile memory cells and the manufacturing process for the peripheral logic circuit thereof. Moreover, the coupling ratio of the above-mentioned prior art non-volatile memory cell structure is still low. It is known that the coupling ratio is basically proportional to the overlapping area between the floating gate and the control gate and is an important factor related to the operation of the non-volatile memory. Therefore, to maintain sufficient overlapping area between the floating gate and the control gate, namely, coupling ratio, the possibility of further miniaturizing the memory cell size is hindered.
In light of the foregoing, there is a need to provide an improved non-volatile memory cell structure that is capable of eliminating the aforementioned problems.